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cy7b9911v 3.3v roboclock+? high speed low voltage programmable skew clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07408 rev. *d revised june 20, 2007 features all output pair skew <100 ps typical (250 max) 3.75 to 110 mhz output operation user selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at 1 ? 2 and 1 ? 4 input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) zero input-to-output delay 50% duty cycle outputs lvttl outputs drive 50 terminated lines operates from a single 3.3v supply low operating current 32-pin plcc package jitter 100 ps (typical) functional description the cy7b9911v 3.3v roboclock+? high speed low voltage programmable skew clock buffer (lvpscb) offers user selectable control over system clock functions. these multiple output clock drivers pr ovide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems. each of the eight indi vidual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50 . they deliver minimal and specified output skews and full swing logic levels (lvttl). each output is hardwired to one of nine delay or function configurations. delay increments of 0.7 to 1.5 ns are deter- mined by the operating frequency with outputs that can skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows external load and cancels the transmission line delay effects. when this ?zero delay? capability of the lvpscb is combined with the selectable output skew functions, you ca n create output-t o-output delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions allow distribution of a low fre quency clock that are multiplied by two or four at the clock destination. this facility minimizes clock distribution difficulty enabling maximum system clock speed and flexibility. test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 filter phase freq det logic block diagram
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 2 of 14 pin configuration pin definitions signal name io description ref i reference frequency input. this input supplies t he frequency and timing against which all functional variations are measured. fb i pll feedback input (typically conn ected to one of the eight outputs). fs i three level frequency range select. see table 1 . 1f0, 1f1 i three level function select inputs for output pair 1 (1q0, 1q1). see table 2 . 2f0, 2f1 i three level function select inputs for output pair 2 (2q0, 2q1). see table 2 . 3f0, 3f1 i three level function select inputs for output pair 3 (3q0, 3q1). see table 2 . 4f0, 4f1 i three level function select inputs for output pair 4 (4q0, 4q1). see table 2 . test i three leve l select. see ?test mode? on page 4 under the ?block diagram description? on page 3. 1q0, 1q1 o output pair 1. see table 2 . 2q0, 2q1 o output pair 2. see table 2 . 3q0, 3q1 o output pair 3. see table 2 . 4q0, 4q1 o output pair 4. see table 2 . v ccn pwr power supply for output drivers. v ccq pwr power supply for internal circuitry. gnd pwr ground. 1 2 3 4323130 17 16 15 14 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f0 fs v ref gnd test 2f1 fb 2q1 2q0 ccq 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 ccn v ccn v 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd plcc cy7b9911v
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 3 of 14 block diagram description phase frequency detector and filter the phase frequency detector and filter blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input. they generate correct ion information to control the frequency of the voltage contro lled oscillator (vco). these blocks, along with the vco, form a phase locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block. it generates a frequency used by the time unit generator to create discrete time units that are selected in the skew select matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the le vel of the fs pin as shown in table 1 . skew select matrix the skew select matrix is comprised of four independent sections. each section has two low skew, high fanout drivers (xq0, xq1), and two corresponding three level function select (xf0, xf1) inputs. ta ble 2 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. table 1. frequency range select and t u calculation [1] fs [2, 3] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min max low 15 30 44 22.7 mid 25 50 26 38.5 high 40 110 16 62.5 t u 1 f nom n ----------------------- - = table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ?4t u divide by 2 divide by 2 low mid ?3t u ?6t u ?6t u low high ?2t u ?4t u ?4t u mid low ?1t u ?2t u ?2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted notes 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid i ndicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ?normal? operating frequency (f nom ) of the v co and time unit generator (see). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see tab l e 2 ). the frequency appearing at the ref and fb inputs is f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs is f nom /2 or f nom /4 when the part is configured for a frequency multiplication using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power up until v cc has reached 2.8v.
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 4 of 14 figure 1 shows the typical outputs with fb connected to a zero skew output. [4] test mode the test input is a three level input. in normal system operation, this pin is connect ed to ground, allowing the cy7b9911v to operate as described in ?block diagram description? on page 3. for testing purposes, any of the three level inputs can have a removable jumper to ground or be tied low through a 100w resistor. this enables an external tester to change the state of these pins. if the test input is forced to its mid or high state, the device operates with its internal phase locked loop disconnected, and input levels supplied to ref directly control all outputs. relative output-to-output functions are the same as in normal mode. in contrast with normal operation (test tied low), all outputs function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. figure 1. the typical outputs with fb connected to a zero skew output t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fb input refinput ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx note 4. fb connected to an output selected for ?zero? skew (that is, xf1 = xf0 = mid).
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 5 of 14 operational m ode descriptions figure 2 shows the lvpscb configured as a zero skew clock buffer. in this mode the cy7b9911v is used as the basis for a low skew clock distribution tree. when all the function select inputs (xf0 , xf1) are left open, each of the outputs are aligned and driv e a terminated transmission line to an independent load. the fb input is tied to any output in this configuration and the operating frequency range is selected with the fs pin. the lo w skew specification, along with the ability to drive terminated transmission lines (w ith impedances as low as 50 ), enables efficient prin ted circuit board design. figure 3 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the lvpscb is programmed to stagger the timing of its outputs. each of the four groups of output pairs is programmed to different output timing. skew timing is adjusted over a wide range in small increments with t he appropriate strapping of the function select pins. in this co nfiguration the 4q0 output is sent back to fb and configured for zero skew. the other three pairs of outputs are programmed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads receive the clock pulse at the same time. in figure 3 the fb input is connected to an output with 0 ns skew (xf1, xf0 = mid) selected. the internal pll synchronizes the fb and ref inputs and aligns their rising edges to make certain that all outputs have precise phase alignment. clock skews are advanced by 6 time units (tu) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ?zero skew?, +tu, and ?tu are defined relative to output figure 2. zero skew and zero delay clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 figure 3. programmable skew clock driver length l1 = l2 l3 < l2 by 6 inches l4 > l2 by 6 inches system clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 6 of 14 groups, and the pll aligns the rising edges of ref and fb, you can create wider output skews by proper selection of the xfn inputs. for example, a +10 tu between ref and 3qx is achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 tu and 3qx skews to +6 tu, a total of +10 tu skew is realized). many other configu- rations are realized by skewing both the outputs used as the fb input and skewing the other outputs. figure 4 shows an example of the in vert function of the lvpscb. in this example, the 4q0 output used as the fb input is programmed for invert (4f0 = 4f 1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this caus es the 1q, 2q, and 3q outputs to become the ?inverted? output s with respect to the ref input. by selecting the output connected to fb, you can have two inverted and six non-inverted outputs or six inverted and two non-inverted outputs. the correct configuration is determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs are also skewed to compensate for varying trace delays independent of inversion on 4q. figure 5 shows the lvpscb configured as a clock multiplier. the 3q0 output is programmed to divide by four and is sent back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz, while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, that results in a 40 mhz waveform at these outputs. no te that the 20 and 40 mhz clocks fall simul- taneously and are out of phase on their rising edge. this enables the designer to use the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency outputs without concern for rising edge skew. the 2q0, 2q1, 1q0, and 1q1 output s run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80 mhz operatio n because that is the frequency of the fastest output. figure 6 shows the lvpscb in a cloc k divider application. 2q0 is sent back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this enables use of the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency without concern for skew mismatch. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15 to 30 mhz range, since the highest frequency output is running at 20 mhz. figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output enables the system de signer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. this function enables each of the two sub systems to clock 180 de grees out of phase, but still is aligned within the skew specification. the divided outputs offer a zero delay divider for portions of the system that divide the clock by ei ther two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, an external divider is added, and the propagation delay of the divider adds to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, allow the lvpscb to mu ltiply the clock rate at the ref input by either two or four. this mode enables the designer to distribute a low frequency clock between va rious portions of the system, and then locally multiply the clock rate to a more suitable figure 4. inverted output connections figure 5. frequency multiplier with skew connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz figure 6. frequency divider connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 7 of 14 frequency, while still maintaining the low skew characteristics of the clock driver. the lvpscb pe rforms all of the functions described in this section at the same time. it can multiply by two and four or divide by two (and four) at the same time. this shifts its outputs over a wide range or maintain zero skew between selected outputs. figure 8 shows the cy7b9911v connected in series to construct a ze ro skew clock distribution tree between boards. delays of the downstream clock buffers are programmed to compensate for the wir e length (that is, select negative skew equal to the wire dela y) necessary to connect them to the master clock source, approxi mating a zero delay clock tree. cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the pll filter. do not connect more than two clock b uffers in a series. figure 7. multi-function clock driver figure 8. board-to-board clock distribution 27.5 mhz distribution clock 110 mhz inverted z 0 27.5 mhz 110 mhz zero skew 110 mhz skewed ?2.273 ns (?4t u ) fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0 system clock z 0 l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 8 of 14 maximum ratings operating outside these boundaries may affect the performance and life of the device. these user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............... .............. ... ?55c to +125c supply voltage to ground potentia l................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v output current into outputs (low)............................. 64 ma static discharge voltage....... ........... ............ ............. > 2001v (mil-std-883, method 3015) latch up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 10% electrical characteristics over the operating range [5] parameter description test conditions cy7b9911v unit min max v oh output high voltage v cc = min, i oh = ?18 ma 2.4 v v ol output low voltage v cc = min, i ol = 35 ma 0.45 v v ih input high voltage (ref and fb inputs only) 2.0 v cc v v il input low voltage (ref and fb inputs only) ?0.5 0.8 v v ihh three level input high voltage (test, fs, xfn) [5] min v cc max 0.87 * v cc v cc v v imm three level input mid voltage (test, fs, xfn) [5] min v cc max 0.47 * v cc 0.53 * v cc v v ill three level input low voltage (test, fs, xfn) [5] min v cc max 0.0 0.13 * v cc v i ih input high leakage current (ref and fb inputs only) v cc = max, v in = max 20 a i il input low leakage current (ref and fb inputs only) v cc = max, v in = 0.4v ? 20 a i ihh input high current (test, fs, xfn) v in = v cc 200 a i imm input mid current (test, fs, xfn) v in = v cc /2 ? 50 50 a i ill input low current (test, fs, xfn) v in = gnd ? 200 a i os short circuit current [7] v cc = max, v out = gnd (25 only) ? 200 ma i ccq operating current used by internal circuitry v ccn = v ccq = max, all input selects open com?l 95 ma mil/ind 100 i ccn output buffer current per output pair [8] v ccn = v ccq = max, i out = 0 ma input selects open, f max 19 ma pd power dissipation per output pair [9] v ccn = v ccq = max, i out = 0 ma input selects open, f max 104 mw notes 5. for more information see group a subgroup testing information . 6. these inputs are normally wired to vcc, gnd, or left unconnect ed (actual threshold voltages vary as a percentage of vcc). int ernal termination resistors hold unconnected inputs at vcc/2. if these inputs are switched, the fu nction and timing of the outputs glitch and the pll may requir e an additional tlock time before all data sheet limits are achieved. 7. cy7b9911v must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room temper ature only. 8. total output current per output pair is approximated by the following expression that includes device current plus load curre nt: cy7b9911v: iccn = [(4 + 0.11f) + [[ ((835 ?3f)/z) + (.0022fc)]n] x 1.1 where f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 fc = f < c 9. total power dissipation per output pair is approximated by th e following expression that includes device power dissipation pl us power dissipation due to the load circuit: pd = [(22 + 0.61f) + [[(1550 + 2.7f)/z) + (.0125fc)]n] x 1.1. (see note 8 for variable definition.)
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 9 of 14 capacitance tested initially and after any design or proce ss changes that may affect these parameters. [10] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.3v 10 pf note 10. applies to ref and fb inputs only. ac test loads and waveforms switching characteristics ? 5 option over the operating range [2, 11] parameter description cy7b9911v-5 unit min typ max f nom operating clock frequency in mhz fs = low [1, 2] 15 30 mhz fs = mid [1, 2] 25 50 fs = high [1, 2 , 3] 40 110 t rpwh ref pulse width high 5.0 ns t rpwl ref pulse width low 5.0 ns t u programmable skew unit see ta ble 1 t skewpr zero output matched-pair skew (xq0, xq1) [13, 14] 0.1 0.25 ns t skew0 zero output skew (all outputs) [13, 15] 0.25 0.5 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [13, 17] 0.6 0.7 ns t skew2 output skew (rise-fall, nomi nal-inverted, divided-divided) [13, 17] 0.5 1.0 ns t skew3 output skew (rise-rise, fall- fall, different class outputs) [17, 17] 0.5 0.7 ns t skew4 output skew (rise-fall, nomi nal-divided, divided-inverted) [13, 17] 0.5 1.0 ns t dev device-to-device skew [12, 18] 1.25 ns t pd propagation delay, ref rise to fb rise ?0.5 0.0 +0.5 ns t odcv output duty cycle variation [19] ?1.0 0.0 +1.0 ns t pwh output high time deviation from 50% [20] 2.5 ns t pwl output low time deviation from 50% [20] 3ns t orise output rise time [20, 21] 0.15 1.0 1.5 ns t ofall output fall time [20, 21] 0.15 1.0 1.5 ns t lock pll lock time [22] 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 ps peak-to-peak [12] 200 ps ttl ac test load ttl input test waveform v cc r1 r2 c l 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v r1=100 r2=100 c l =30pf (includes fixture and probe capacitance) figure 9. ac test loads and waveforms
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 10 of 14 switching characteristics ? 7 option over the operating range [2, 11] parameter description cy7b9911v-7 unit min typ max f nom operating clock frequency in mhz fs = low [1, 2] 15 30 mhz fs = mid [1, 2] 25 50 fs = high [1, 2 , 3] 40 110 t rpwh ref pulse width high 5.0 ns t rpwl ref pulse width low 5.0 ns t u programmable skew unit see table 1 t skewpr zero output matched pair skew (xq0, xq1) [13, 14] 0.1 0.25 ns t skew0 zero output skew (all outputs) [13, 15] 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [13, 17] 0.6 1.0 ns t skew2 output skew (rise-fall, no minal-inverted, divided-divided) [13, 17] 1.0 1.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [13, 17] 0.7 1.2 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [13, 17] 1.2 1.7 ns t dev device-to-device skew [12, 18] 1.65 ns t pd propagation delay, ref rise to fb rise ?0.7 0.0 +0.7 ns t odcv output duty cycle variation [19] ?1.2 0.0 +1.2 ns t pwh output high time deviation from 50% [20] 3ns t pwl output low time deviation from 50% [20] 3.5 ns t orise output rise time [20, 21] 0.15 1.5 2.5 ns t ofall output fall time [20, 21] 0.15 1.5 2.5 ns t lock pll lock time [22] 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 ps peak [12] 100 200 ps notes 11. test measurement levels for the cy7b9911v are ttl levels (1.5 v to 1.5v). test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 12. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 13. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same tu de lay is selected when all are loaded with 30 pf and terminated with 50 to vcc/2 (cy7b9911v). 14. tskewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0tu. 15. tskew0 is defined as the skew between outputs when they are selected for 0tu. other outputs are divided or inverted but not shifted. 16. cl=0 pf. for cl=30 pf, tskew0=0.35 ns. 17. there are three classes of outputs: nominal (multiple of tu delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and d ivided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 18. tdev is the output-to-output skew between any two devices oper ating under the same conditions (vcc ambient temperature, air flow, and so on.) 19. todcv is the deviation of t he output from a 50% duty cycle. output pulse width variations are included in tskew2 and tskew4 specifications. 20. specified with outputs loaded with 30 pf for the cy7b9911v-5 and -7 devices. devices are terminated through 50 to vcc/2.tpwh is measured at 2.0v. tpwl is measured at 0.8v. 21. torise and tofall measured between 0.8v and 2.0v. 22. tlock is the time that is required befor e synchronization is achieved. this specification is valid only after vcc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until tpd is within specified limits.
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 11 of 14 ac timing diagrams t odcv t odcv t ref ref fb q other q inverted q ref divided by 2 ref divided by 4 t rpwh t rpwl t pd t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 t skew3, 4 t skew3, 4 t skew3, 4 t skew1,3, 4 t skew2, 4 t jr
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 12 of 14 ordering information accuracy (ps) ordering code package type operating range 500 cy7b9911v-5jc 32-pb plastic leaded chip carrier commercial 500 cy7b9911v-5jct 32-pb plastic leaded chip carrier ? tape and reel commercial 700 cy7b9911v-7jc [23] 32-pb plastic leaded chip carrier commercial 700 cy7b9911v-7jct [23] 32-pb plastic leaded chip carrier ? tape and reel commercial pb-free 500 CY7B9911V-5JXC 32-pb plastic leaded chip carrier commercial 500 CY7B9911V-5JXCt 32-pb plastic leaded chip carrier ? tape and reel commercial 700 cy7b9911v-7jxc [23] 32-pb plastic leaded chip carrier commercial 700 cy7b9911v-7jxct [23] 32-pb plastic leaded chip carrier ? tape and reel commercial note 23. parts not recommended for the new design.
cy7b9911v 3.3v roboclock+? document number: 38-07408 rev. *d page 13 of 14 package diagram figure 10. 32-pin plastic leaded chip carrier j65 51-85002-*b
document number: 38-07408 rev. *d revised june 20, 2007 page 14 of 14 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by phil ips. roboclock+ is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7b9911v 3.3v roboclock+? ? cypress semiconductor corporation, 2002-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7b9911v 3.3v roboclock+? high speed low voltage programmable skew clock buffer document number: 38-07408 rev. ecn no. issue date orig. of change description of change ** 114350 3/20/02 dsg change from specif ication number: 38-00765 to 38-07408 *a 299713 see ecn rgl added tape and reel and pb-free devices in the ordering information table added 100 ps typical value for jitter (peak) *b 404630 see ecn rgl minor change: added a note in ordering table that pb-free is in pure sn *c 1199925 see ecn kvm/aesa added no te 23: parts not recommended fo r the new design in ordering information table *d 1286064 see ecn aesa change status to final

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